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5.2.3.2跳过和重置功能
可以重置帧处理程序或从任何状态跳过无效帧。这可以通过将一个写入RST或SKIP来实现
FHC寄存器的位。跳过帧会导致帧处理程序忽略传入消息的其余部分，而不会触发任何
附加中断。在接收到其余无效消息或检测到超时后，将进行软重置。跳过帧没有
对循环计时器的影响。重置帧会立即将帧处理程序重置为其空闲状态，并导致周期重置
计时器。
5.3中断处理
该芯片利用两种中断处理模式。可以使用INT寄存器中的IMODE位切换活动模式。中断模式
默认情况下，1处于活动状态。
5.3.1模式1
中断在SPI状态下的WURQ、RXRDY、TXRDY或TOUT位的上升沿触发。如果CQ配置为输入
在SIO模式下，中断也会在RXD位的任何边缘触发。SPI状态中状态位的变化也会触发中断，
取决于IMSK寄存器设置。触发条件可以是帧传输或接收的开始或达到定义的填充
缓冲区的级别。中断总是在完全接收到帧后触发。
另一个触发条件是STAT寄存器中值的任何更改。这就是微控制器应始终处理中断的原因
通过读回STAT寄存器。读取状态寄存器时，中断被清除。
5.3.2模式2
中断触发条件与中断模式1中描述的相同。模式2在处理中断的方式上有所不同。首先
中断源可以通过读取INT寄存器来确定。然后，用户需要主动清除中断。完成了
通过将一写入INT寄存器中的适当位ISTAT、ICH1或ICH2。INTX引脚保持激活状态，直到所有中断
已清除。
空闲接收传输
传输完成
重置已触发
重置已触发
主消息的个字节开始
缓冲设备消息
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CM3120
存档信息
存档信息
5.3.3中断屏蔽
为了减少帧处理程序模式中触发的中断量，用户可以在特定时间停用中断触发
IMSK寄存器中的条件。表5列出了所有帧处理程序中断。
MSG中断始终处于活动状态。默认情况下，所有其他中断都被屏蔽。如果LVL中断处于活动状态，则在以下情况下触发中断：
输入缓冲区达到定义的填充级别。可以在BLVL寄存器中查询缓冲字符的当前数量。的阈值
触发LVL中断的缓冲字符在TRSH寄存器中配置。
图5。中断触发位置
也可以屏蔽STAT寄存器的短检测（SD）中断。否则，一旦出现短路，就会触发中断
检测到。
5.4保护特性
CM3120 IO链路主机集成了各种功能，以保护IO链路主机和连接的IO链路设备。不同的
配置选项允许用户采取单独的安全措施并防止损坏。
5.4.1电流传感
5.4.1.1内部/外部模式
有两种可能的方法用于检测IO链路电源电压处的高负载-内部和外部电流
传感机构。这两种机制不能同时激活。用户必须选择每个应用程序应使用哪一个
频道电流传感模式由CFG寄存器中的SDINT位配置。STAT寄存器中的SD位和SDX引脚
始终反映当前传感状态。
内部电流传感机制不需要任何外部电路即可工作，但仅限于检测电流IMH
以及CM3120 CQ引脚处具有固定电流阈值的IMLS。无法检测到来自连接设备的高电流IDEV。
因此，在这种模式下，设备的短路保护功能不可行。仍然可以使用外部NMOS晶体管。
外部电流传感可以检测连接设备的CQ引脚和IDEV处的高电流IMH和IML。外部分流器
对于400 mA的电流阈值，需要施加0.5Ω的典型电阻。可以调整高电流检测
通过改变分流电阻值来确定阈值。分流器上的压降定义为200 mV。分流器上的电流感应
外部NMOS晶体管允许使用短路保护功能。
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5.2.3.2 Skip and reset function
It is possible to reset the frame handler or skip an invalid frame from any state. This can be done by writing one to the RST or the SKIP
bit of the FHC register. Skipping a frame causes the frame handler to ignore the rest of an incoming message, without triggering any
additional interrupt. A soft reset is done after receiving the rest of invalid message or if a timeout was detected. Skipping a frame has no
effect on the cycle timer. Resetting a frame immediately resets the frame handler into its idle state and also causes a reset of the cycle
timer.
5.3 Interrupt handling
The chip utilizes two modes of interrupt handling. The active mode can be switched with the IMODE bit in the INT register. Interrupt mode
1 is active by default.
5.3.1 Mode 1
Interrupts are triggered on rising edges of the WURQ, RXRDY, TXRDY, or TOUT bits in the SPI Status. If CQ is configured as an input
in SIO mode, interrupts are also triggered on any edge of the RXD bit. Changes of the STATE bits in the SPI Status also trigger interrupts,
depending on the IMSK register settings. Trigger conditions can be the start of frame transmission or reception or reaching a defined fill
level of the buffer. An interrupt is always triggered after a frame is completely received.
Another trigger condition is any change of values in the STAT register. This is why the microcontroller should always deal with an interrupt
by reading back the STAT register. The interrupt is cleared while reading the status register.
5.3.2 Mode 2
The interrupt triggering conditions are the same as described in Interrupt mode 1. Mode 2 differs in how interrupts are handled. First, the
interrupt origin can be determined by reading the INT register. The interrupt then needs to be actively cleared by the user. This is done
by writing a one to the appropriate bit ISTAT, ICH1, or ICH2 in the INT register. The INTX pin remains in its active state until all interrupts
are cleared.
IDLE RECEIVE TRANSMIT
transmission done
reset triggered
reset triggered
start of master message first byte of
device message buffered
11 NXP Semiconductors
CM3120
ARCHIVE INFORMATION
ARCHIVE INFORMATION
5.3.3 Interrupt masking
To reduce the amount of triggered interrupts in frame handler mode, the user can deactivate the triggering of interrupts at certain
conditions in the IMSK register. All frame handler interrupts are listed in the Table 5.
The MSG interrupt is always active. By default, all other interrupts are masked. If the LVL interrupt is active, an interrupt is triggered if the
input buffer reaches a defined fill level. The current amount of buffered characters can be queried in the BLVL register. The threshold for
buffered characters which triggers the LVL interrupt is configured in the TRSH register.
 Figure 5. Interrupt Trigger Positions
It is also possible to mask the short detected (SD) interrupt of the STAT register. Otherwise an interrupt gets triggered as soon as a short
is detected.
5.4 Protection features
The CM3120 IO-Link Master integrates various features to protect the IO-Link master and connected IO-Link devices. Different
configuration options allow the user to take individual safety measures and to prevent damage.
5.4.1 Current sensing
5.4.1.1 Internal/external mode
There are two possible methods implemented to detect a high load at the IO-Link supply voltage - an internal and an external current
sensing mechanism. Both mechanisms cannot be active at the same time. The user has to choose, which one should be used for each
channel. The current sensing mode is configured by the SDINT bit in the CFG register. The SD bit in the STAT register and the SDX pins
always reflect the current sensing state.
The internal current sensing mechanism does not need any external circuitry to work, but has the limitation to only detect currents IMHS
and IMLS at the CM3120 CQ pin with a fixed current threshold. High currents IDEV from a connected device cannot be detected.
Therefore the short protection feature for devices is not feasible in this mode. The usage of an external NMOS transistor is still possible.
The external current sensing can detect high currents IMHS and IMLS at the CQ pin and IDEV of a connected device. External shunts
with a typical resistance of 0.5 Ω needs to be applied for a current threshold of 400 mA. It is possible to adjust the high current detection
threshold by changing the shunts resistance value. The voltage drop over the shunt is defined with 200 mV. Current sensing over a shunt
and an external NMOS transistor allow the usage of the short protection feature.