转换被选通关闭，直到下一次扫描开始，AIGATE才将其重新选通。SISOURCE信号任何PFI引脚都可以接收SISOURCE信号作为输入，该信号在I/O连接器上不能作为输出。SI2使用SISOURCE作为时钟，为STARTSCAN信号的生成计时。您必须在液位检测模式下配置您选择作为SISOURCE源的PFI引脚。您可以将PFI引脚的极性选择配置为激活高电平或激活低电平。大允许频率为20 MHz，小脉冲宽度为23 ns高或低。没有低频率限制。除非您选择一些外部源，否则20 MHz或100 kHz内部时基会生成SISOURCE。图4-19显示了SISOURCE的定时要求。图4-19：。SISOURCE Signal Timing SCANCLK Signal SCANCLK是一种仅输出的信号，它在a/D转换开始后产生一个前沿约为50到100 ns的脉冲。该输出的极性是软件可选择的，但其通常配置为低到高的前沿可以对外部AI多路复用器进行时钟，指示何时对输入信号进行了采样并可以删除。该信号的脉冲宽度为450 ns，并且已启用软件。注：SCANCLK极性从低到高，不能使用NI-DAQ以编程方式更改。tw=23 ns小tp=50 ns小tp tw tw第4章连接信号©National Instruments Corporation 4-27 NI PCI-6110/6111用户手册图4-20显示了SCANCLK的计时。图4-20：。SCANCLK信号定时EXTSTROBE*信号EXTSTROBE*是在硬件选通模式下生成单个脉冲或八个脉冲序列的仅输出信号。外部设备可以使用此信号锁定信号或触发事件。在单脉冲模式下，软件控制EXTSTROBE*的电平。10µs和1.2µs时钟可用于在硬件选通模式下生成八个脉冲序列。注：EXTSTROBE*无法通过NI-DAQ启用。图4-21显示了硬件选通模式EXTSTROBE*信号的定时。图4-21：。EXTSTROBE*信号定时波形生成定时连接为NI PCI-6110/6111定义的模拟组由WFTRIG、UPDATE*和UISOURCE控制。

conversions are being gated off, AIGATE does not gate them back on until the beginning of the next scan. SISOURCE Signal Any PFI pin can receive as an input the SISOURCE signal, which is not available as an output on the I/O connector. The SI2 uses SISOURCE as a clock to time the generation of the STARTSCAN signal. You must configure the PFI pin you select as the source for SISOURCE in the level-detection mode. You can configure the polarity selection for the PFI pin for either active high or active low. The maximum allowed frequency is 20 MHz, with a minimum pulse width of 23 ns high or low. There is no minimum frequency limitation. Either the 20 MHz or 100 kHz internal timebase generates SISOURCE unless you select some external source. Figure 4-19 shows the timing requirements for SISOURCE. Figure 4-19. SISOURCE Signal Timing SCANCLK Signal SCANCLK is an output-only signal that generates a pulse with the leading edge occurring approximately 50 to 100 ns after an A/D conversion begins. The polarity of this output is software-selectable, but it is typically configured so that a low-to-high leading edge can clock external AI multiplexers indicating when the input signal has been sampled and can be removed. This signal has a 450 ns pulse width and is software enabled. Note SCANCLK polarity is low-to-high and cannot be changed programmatically using NI-DAQ. tw = 23 ns minimum tp = 50 ns minimum tp tw tw Chapter 4 Connecting Signals © National Instruments Corporation 4-27 NI PCI-6110/6111 User Manual Figure 4-20 shows the timing for SCANCLK. Figure 4-20. SCANCLK Signal Timing EXTSTROBE* Signal EXTSTROBE* is an output-only signal that generates either a single pulse or a sequence of eight pulses in the hardware-strobe mode. An external device can use this signal to latch signals or to trigger events. In the single-pulse mode, software controls the level of EXTSTROBE*. A 10 µs and a 1.2 µs clock are available for generating a sequence of eight pulses in the hardware-strobe mode. Note EXTSTROBE* cannot be enabled through NI-DAQ. Figure 4-21 shows the timing for the hardware-strobe mode EXTSTROBE* signal. Figure 4-21. EXTSTROBE* Signal Timing Waveform Generation Timing Connections The analog group defined for the NI PCI-6110/6111 is controlled by WFTRIG, UPDATE*, and UISOURCE.