VMEbus接口提供选项A24：D16从接口和
支持8位（字节）和16位（字）读、写和读修改写
数据传输。接口由地址解码器、数据
收发器和数据传输控制逻辑。电路板选择为
由前面板上的绿色选择二极管指示，该二极管点亮
模块上数据传输周期的持续时间。详细说明
第2.6段给出了VMEbus接口的时序图。
当数据写入RAM时，将为每个字节生成奇偶校验位
与数据一起存储。从RAM读取数据时，每个
检查字节和奇偶校验位。取决于奇偶校验的结果
检查，返回数据传输确认或总线错误信号
至VMEbus主机。如果检测到奇偶校验错误，则红色错误二极管
打开前面板上的。直到完成
下一次成功的读或写访问。
为了确保数据保留在内存中，刷新控制器执行
动态RAM设备中每15.6微秒仅RAS刷新一次
在升序行地址上。内存刷新独立于VMEbus
信号。控制逻辑在内存刷新和cata传输之间进行仲裁
循环并生成本地控制和定时信号
不考虑VMEbus数据传输握手

The VMEbus interface provides an option A24:D16 slave interface and supports 8-bit (byte) and 16-bit (word) read, write and read-modify-write data transfers. The interface consists of the address decoder, the data transceivers, and data transfer control logic. A board selection is indicated by the green SELECT diode on the front panel, which is lit for the duration of a data transfer cycle on the module. A detailed description and timing diagrams of the VMEbus interface are given in Paragraph 2.6. When data is written into RAM, a parity bit is generated for each byte and stored along with the data. When data is read from RAM, the parity of each byte and the parity bit are checked. Depending on the result of the parity check, either a data transfer acknowledge or a bus error signal is returned to the VMEbus master. If a parity error is detected, the red ERROR diode on the front panel is turned on. It remains lit until the completion of the next successful read or write access. To ensure data retention in the memory, a refresh controller performs a RAS-only refresh cycle in the dynamic RAM devices every 15.6 microseconds on ascending row addresses. Memory refresh is independent of VMEbus signals. Control logic arbitrates between memory refresh and cata transfer cycles and generates the local control and timing signals totally irrespective of the VMEbus data transfer handshake